用Quartus II設(shè)計(jì)電子琴
,單擊此處編輯母版標(biāo)題樣式,單擊此處編輯母版文本樣式,第二級(jí),第三級(jí),第四級(jí),第五級(jí),*,電子琴設(shè)計(jì),設(shè)計(jì)要求,設(shè)計(jì)一個(gè)八音電子琴。,由鍵盤(pán)輸入控制音響,同時(shí)可自動(dòng)演奏樂(lè)曲。,用戶可以將自己編制的樂(lè)曲存入電子琴,演奏時(shí)可選擇鍵盤(pán)輸入樂(lè)曲或者已存入的樂(lè)曲。,系統(tǒng)組成,系統(tǒng)由數(shù)控分頻器和樂(lè)曲存儲(chǔ)模塊組成。,數(shù)控分頻器對(duì),FPGA,的基準(zhǔn)頻率進(jìn)行分頻,得到與各個(gè)音階對(duì)應(yīng)的頻率輸出。,樂(lè)曲存儲(chǔ)模塊產(chǎn)生節(jié)拍控制和音階選擇信號(hào),即在此模塊中可存放一個(gè)樂(lè)曲曲譜真值表,由一個(gè)計(jì)數(shù)器來(lái)控制此真值表的輸出,而由計(jì)數(shù)器的計(jì)數(shù)時(shí)鐘信號(hào)作為樂(lè)曲節(jié)拍控制信號(hào)。,模塊設(shè)計(jì),1.,頂層模塊的設(shè)計(jì),2.,自動(dòng)演奏模塊,(,automusic,),的設(shè)計(jì),3.,音調(diào)發(fā)生器,(tone),模塊的設(shè)計(jì),4.,數(shù)控分頻模塊(,speaker,)的設(shè)計(jì),1.,頂層模塊的設(shè)計(jì),頂層模塊由樂(lè)曲自動(dòng)演奏(,automusic,),音調(diào)發(fā)生器(,tone,)和數(shù)控分頻器(,speaker,)三個(gè)模塊組成。,其中樂(lè)曲演奏部分又包括了鍵盤(pán)編碼。,設(shè)置一個(gè)自動(dòng)演奏,/,鍵盤(pán)輸入切換,auto,,即當(dāng),auto=“0”,時(shí),選擇自動(dòng)演奏音樂(lè)存儲(chǔ)器里面的樂(lè)曲,,auto=“1”,時(shí),選擇鍵盤(pán)輸入的信號(hào)。,頂層設(shè)計(jì)原理圖,2.,自動(dòng)演奏模塊,(,automusic,),的設(shè)計(jì),音樂(lè)存儲(chǔ)模塊的作用是產(chǎn)生,8,位發(fā)聲控制輸入,index,。,當(dāng),auto,為“,0”,時(shí),由存儲(chǔ)在此模塊中的,8,位二進(jìn)制數(shù)作為發(fā)聲控制輸入,可自動(dòng)演奏樂(lè)曲。,此模塊的,VHDL,程序中包括兩個(gè)進(jìn)程,首先是對(duì)時(shí)基脈沖進(jìn)行分頻得到,4Hz,的脈沖,作為第二個(gè)進(jìn)程的時(shí)鐘信號(hào),它用來(lái)控制每個(gè)音階之間的停頓時(shí)間,,1/4=0.25s,;第二個(gè)進(jìn)程是音樂(lè)的存儲(chǔ),可根據(jù)需要編寫(xiě)不同的樂(lè)曲。,3.,音調(diào)發(fā)生器,(tone),模塊的設(shè)計(jì),音調(diào)發(fā)生器的作用是產(chǎn)生獲得音階的分頻預(yù)置值。,當(dāng),8,位發(fā)聲控制輸入,index,中的某一位為高電平時(shí),則對(duì)應(yīng)某一音階的數(shù)值將在端口,tone,輸出,該數(shù)值即為該音階的分頻預(yù)置值,分頻預(yù)置值控制數(shù)控分頻器來(lái)對(duì),4MHz,的脈沖進(jìn)行分頻,由此可得到每個(gè)音階對(duì)應(yīng)的頻率。,例如輸入,index=“00000010”,,即對(duì)應(yīng)的按鍵是,2,,產(chǎn)生的分頻系數(shù)便是,6809,;,code,輸出對(duì)應(yīng)該音階簡(jiǎn)譜的顯示數(shù)碼;,high,輸出指示音階高,8,度,低電平有效。,4.,數(shù)控分頻模塊(,speaker,)的設(shè)計(jì),數(shù)控分頻模塊對(duì)時(shí)基脈沖進(jìn)行分頻,得到與,1,、,2,、,3,、,4,、,5,、,6,、,7,七個(gè)音符對(duì)應(yīng)頻率。,該模塊的,VHDL,程序中包含了三個(gè)進(jìn)程。,首先對(duì),FPGA,的,32MHz,的時(shí)基脈沖進(jìn)行分頻得到,8MHz,的脈沖,,然后按照,tone1,輸入的分頻系數(shù)對(duì),8MHz,的脈沖再次分頻,得到所需要的音符頻率。,第三個(gè)進(jìn)程的作用是在音調(diào)輸出時(shí)再進(jìn)行二分頻,將脈沖展寬,使揚(yáng)聲器有足夠發(fā)聲功率。,電子琴程序設(shè)計(jì)與仿真,電子琴程序設(shè)計(jì)與仿真,1.,頂層程序與仿真,2.,音階發(fā)生器程序與仿真,3.,數(shù)控分頻模塊程序與仿真,4.,自動(dòng)演奏模塊程序與仿真,1.,頂層程序與仿真,-,文件名:,top.vhd,-,功能:頂層文件,-,最后修改日期:,2004.3.20,library IEEE;,use IEEE.STD_LOGIC_1164.ALL;,use IEEE.STD_LOGIC_ARITH.ALL;,use IEEE.STD_LOGIC_UNSIGNED.ALL;,entity top is,Port(clk32MHz :in,std_logic,;-32MHz,系統(tǒng)時(shí)鐘,handTOauto,:in,std_logic,;-,鍵盤(pán)輸入,/,自動(dòng)演奏,code1 :out std_logic_vector(6,downto,0);-,音符顯示信號(hào),index1 :in std_logic_vector(7,downto,0);-,鍵盤(pán)輸入信號(hào),high1 :out,std_logic,;-,高低音節(jié)信號(hào),spkout,:out,std_logic,);-,音頻信號(hào),end top;,architecture Behavioral of top is,component,automusic,Port(,clk,:in,std_logic,;,Auto:in,std_logic,;,index2:in std_logic_vector(7,downto,0);,index0:out std_logic_vector(7,downto,0);,end component;,component tone,Port(index:in std_logic_vector(7,downto,0);,code:out std_logic_vector(6,downto,0);,high:out,std_logic,;,tone0:out integer range 0 to 2047);,end component;,component speaker,Port(clk1:in,std_logic,;,tone1:in integer range 0 to 2047;,spks,:out,std_logic,);,end component;,signal tone2:integer range 0 to 2047;,signal indx:std_logic_vector(7,downto,0);,begin,u0:automusic port,map(clk,=clk32MHZ,index2=index1,index0=,indx,Auto,=,handtoAuto,);,u1:tone port,map(index,=indx,tone0=tone2,code=code1,high=high1);,u2:speaker port map(clk1=clk32MHZ,tone1=tone2,spks=,spkout,);,end Behavioral;,(頂層文件仿真圖),2.,音階發(fā)生器程序與仿真,-,文件名:,tone.vhd,。,-,功能:音階發(fā)生器程序。,-,最后修改日期:,2004.4.13,。,library IEEE;,use IEEE.STD_LOGIC_1164.ALL;,use IEEE.STD_LOGIC_ARITH.ALL;,use IEEE.STD_LOGIC_UNSIGNED.ALL;,entity tone is,Port(index:in std_logic_vector(7,downto,0);-,音符輸入信號(hào),code :out std_logic_vector(6,downto,0);-,音符顯示信號(hào),high :out,std_logic,;-,高低音顯示信號(hào),tone0:out integer range 0 to 2047);-,音符的分頻系數(shù),end tone;,architecture Behavioral of tone is,begin,search:,process(index,),-,此進(jìn)程完成音符到音符的分頻系數(shù)譯碼,音符的顯示,高低音階,begin,case index is,when 00000001=tone0=773;code=1001111;high tone0=912;code=0010010;high tone0=1036;code=0000110;high tone0=1116;code=1001100;high tone0=1197;code=0100100;high tone0=1290;code=0100000;high tone0=1372;code=0001111;high tone0=1410;code=0000000;high tone0=2047;code=0000001;high=0;,end case;,end process;,end Behavioral;,(音階發(fā)生器仿真圖),3.,數(shù)控分頻模塊程序與仿真,-,文件名:,speaker.vhd,。,-,功 能:實(shí)現(xiàn)數(shù)控分頻。,-,最后修改日期:,20004.3.19,。,library IEEE;,use IEEE.STD_LOGIC_1164.ALL;,use IEEE.STD_LOGIC_ARITH.ALL;,use IEEE.STD_LOGIC_UNSIGNED.ALL;,entity speaker is,Port(clk1 :in,std_logic,;-,系統(tǒng)時(shí)鐘,tone1:in integer range 0 to,2047,;-,音符分頻系數(shù),spks,:out,std_logic,);-,驅(qū)動(dòng)揚(yáng)聲器的音頻信號(hào),end speaker;,architecture Behavioral of speaker is,signal,preclk,fullspks:std_logic,;,begin,pulse1:process(clk1),-,此進(jìn)程對(duì)系統(tǒng)時(shí)鐘進(jìn)行,4,分頻,variable,count:integer,range 0 to 8;,begin,if clk1event and clk1=1 then count:=count+1;,if count=2 then,preclk,=1;,elsif,count=4 then,preclk,=0;count:=0;,end if;,end if;,end process pulse1;,genspks:process(preclk,tone1)-,此進(jìn)程按照,tone1,輸入的,-,分頻系數(shù)對(duì),8MHz,的脈沖再次分頻,得到所需要的音符頻率,variable count11:integer range 0 to 2047;,Begin,if,preclkevent,and,preclk,=1 then,if count11tone1 then,count11:=count11+1;fullspks=1;,else count11:=0;fullspks=0;,end if;,end if;,end process;,delaysps:process(fullspks,)-,此進(jìn)程對(duì),fullspks,進(jìn)行,2,分頻,variable count2:,std_logic,:=0;,begin,if,fullspksevent,and,fullspks,=1 then,count2:=not count2;,if count2=1 then,spks,=1;,else,spks,=0;,end if;,end if;,end process;,end Behavioral,;,(數(shù)控分頻模塊仿真圖),4.,自動(dòng)演奏模塊程序與仿真,-,文件名:,automusic.vhd,-,功 能:實(shí)現(xiàn)自動(dòng)演奏功能。,-,最后修改日期:,2004.3.19,。,library IEEE;,use IEEE.STD_LOGIC_1164.ALL;,use IEEE.STD_LOGIC_ARITH.ALL;,use IEEE.STD_LOGIC_UNSIGNED.ALL;,entity,automusic,is,Port(,clk,Auto,:in,std_logic,;-,系統(tǒng)時(shí)鐘;鍵盤(pán)輸入,/,自動(dòng)演奏,index2:in std_logic_vector(7,downto,0);-,鍵盤(pán)輸入信號(hào),index0:out std_logic_vector(7,downto,0);-,音符信號(hào)輸出,end,automusic,;,architecture Behavioral of,automusic,is,signal count0:integer range 0 to 31;-change,signal clk2:std_logic;,begin,pulse0:process(clk,Au